Analog Layout Intern

Your Team, Your Impact

Marvell Central Engineering (CE) develops Marvell's most advanced high-speed SerDes (HSS) and die-to-die (D2D) IP. These IPs power AI and cloud data center infrastructure, including custom silicon (XPU and attach), switching, storage, and optical interconnect. As the engine of the company, Central Engineering provides the foundational technology behind Marvell's business units.

As an Analog Layout Intern with Marvell, you'll be a member of the Central Engineering business group. You'll be part of an analog team making a big impact on this organization. Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, while also having the time and freedom to dive deep into the details of your specialization on most projects.

What You Can Expect

As an Analog Layout Intern on the AMS team, you will support the layout implementation of analog and mixed-signal integrated circuits, learning how a circuit designer's schematic becomes a physical layout that meets performance, area, and reliability requirements. Projects vary with the product cycle and your own interests, and you will be exposed to a range of IC design skills and tools. Your responsibilities will include:

• Learn the analog design and layout flow, and how analog layout differs from digital physical design.
• Create layouts for basic analog cells (for example comparators and OTAs) in advanced nodes, following analog requirements such as device matching, symmetry, shielding, and layout-dependent effects.
• Assist with floorplanning, placement, and routing of analog and mixed-signal blocks under the guidance of experienced engineers.
• Run physical verification (DRC, LVS, antenna) and help resolve issues, with support from your mentor.
• Learn about parasitic awareness and EM/IR considerations, and work with circuit designers to optimize the layout.
• Use industry-standard tools such as Cadence Virtuoso and Calibre, in a Linux environment.
• Meet regularly with your paired circuit designer and layout team, share progress, and document your work.

What We're Looking For

• Currently pursuing a Bachelor's degree in Electronics, Electrical, or Telecommunications Engineering, Mechatronics, Computer Engineering, or a related field (expected to graduate in 2027)
• Basic understanding of semiconductor devices, CMOS technology, and electronic circuits.
• Strong passion to learn and grow expertise in analog layout.
• Good analytical and problem-solving skills, with attention to detail.
• Self-motivated, willing to learn new technologies, and able to work effectively in a team.
• Good English communication skills.

Nice to Have

• Coursework or projects in analog circuits, VLSI, or IC design.
• Familiarity with Cadence Virtuoso, Calibre DRC/LVS, or similar layout and verification tools.
• Basic knowledge of Linux and scripting (Python, Tcl, or SKILL).

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S.

Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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